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in Verilog on simulating the output equals zzzzzz
Category : Programming Languages

The code is very simple, having bunch of ifs to put a certain value in the variable BUS, the problem that on simulating, the BUS output equals : zzzzzzzzzzzzzzzz
while it's supposed to have certain values corresponding to the if case.


module Bus (AR_OUT, IR_OUT, DR_OUT, PC_OUT, AC_OUT, MEM_OUT, read, S, BUS);
input [11:0]AR_OUT ;
input [11:0]PC_OUT ;
input

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