Why does makefile recompiles everything when a headerfile is changed?

Why does makefile recompiles everything when a headerfile is changed?

By : HarishSingh
Date : November 21 2020, 04:01 AM
will be helpful for those in need You have a rule that says that all .o files built from .c files also depend on the contents of $(DEPS)
code :
%.o: %.c $(DEPS)
    $(CC) -c $(CFLAGS) $< -o $@
DEPS=main.h a.h b.h c.h d.h
a_functions.o: a.h
main.o: a.h b.h
    makedepend -- $(CFLAGS) -- $(SRCS)

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Makefile always recompiles

Makefile always recompiles

By : programmer91
Date : March 29 2020, 07:55 AM
will help you i am having a hard time with the Makefile below. It always recompiles because it is looking for the objects in "source/" instead of "objects/". , This should do it:
code :
    $(LD) $(LD_FLAGS) $^ $(LIB)

$(FP_OBJ) : $(OBJ_DIR)%.o : $(SRC_DIR)%.cpp
    $(CC) $(CC_FLAGS) $@ $<
$(OBJ) : $(SRC)
    $(CC) $(CC_FLAGS)$(OBJ_DIR)$@ $(SRC_DIR)$*.cpp
Eclipse CDT generate makefile with makefile.init, makefile.defs, makefile.targets

Eclipse CDT generate makefile with makefile.init, makefile.defs, makefile.targets

By : user2344720
Date : March 29 2020, 07:55 AM
this will help The three includes are intended for your sake. If you need to compile something proprietary manually, or copy files or anything you can come up with before the main program is compiled, you create the file makefile.init in the source directory and put your makefile-stuff in here.
The same applies to the other files just at other times in the compile chain.
Makefile recompiles after cleaning objects (but not the name target)

Makefile recompiles after cleaning objects (but not the name target)

By : dexmond
Date : March 29 2020, 07:55 AM
wish help you to fix your issue The $(NAME) dependecy in the all rule is NOT satisfied, because $(NAME) depends on $(OBJS) - and $(OBJS) does not exist (after make clean). This is how make works. If any dependencies don't exists or are newer than the target - the dependecies need to be regenerated (and in turn - the target).
For example: program --> program.o --> (program.c, program.h)
Makefile that only recompiles changed objects?

Makefile that only recompiles changed objects?

By : rosyheart
Date : March 29 2020, 07:55 AM
I hope this helps . Modified your Makefile to:
Automatically generate header dependencies. Re-build and re-link when Makefile changes.
code :
CXX := g++
LD := ${CXX}
CXXFLAGS := -Wall -Wextra -std=gnu++14 -pthread
LDFLAGS := -pthread

exes :=

# Specify EXEs here begin.

Main.SOURCES := Main.cpp initializeArray.cpp printArray.cpp
exes += Main

# Specify EXEs here end.

all: $(exes)


get_objects = $(patsubst %.cpp,%.o,${${1}.SOURCES})
get_deps = $(patsubst %.cpp,%.d,${${1}.SOURCES})

# Links executables.
${exes} : % : $$(call get_objects,$$*) Makefile
    ${LD} -o $@ $(filter-out Makefile,$^) ${LDFLAGS}

# Compiles C++ and generates dependencies.
%.o : %.cpp Makefile
    ${CXX} -o $@ -c ${CPPFLAGS} ${CXXFLAGS} -MP -MD $<

# Include the dependencies generated on a previous build.
-include $(foreach exe,${exes},$(call get_deps,${exe}))

.PHONY: all
Makefile that recompiles only if its dependency actually changed

Makefile that recompiles only if its dependency actually changed

By : Danial Zaghi
Date : March 29 2020, 07:55 AM
To fix the issue you can do What you suggested doing in your last paragraph is the usual way of conditionally rebuilding targets only if a particular dependency has actually changed, rather than just if that dependency's time stamp has changed. In the rule that generates the particular dependency, you generate it as a temporary file, check to see if its contents have changed and if so replace the target of the rule with the temporary file. Notably, GCC has been doing this in its makefiles as long as I can remember. It generates source code and header files with things like tables and pattern recognizers that often don't change when one of their dependencies does. Stopping targets that are dependants of these generated files from being rebuilt can make a big difference in build times.
So for your example makefile you could do something like:
code :
date.h: FORCE
        echo "#define DATE" '"' $$(date '+%D-%H:%M') '"' > date.h.tmp
        if test -r date.h;                                              \
        then                                                            \
                cmp date.h.tmp date.h || mv -f date.h.tmp date.h;       \
        else                                                            \
                mv date.h.tmp date.h;                                   \
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