Aligning doubles on 8-byte boundaries?

Aligning doubles on 8-byte boundaries?

By : Zouaghi Mariem
Date : October 17 2020, 11:12 AM
I wish this helpful for you Is there a common portable idiom in numerics code (I'm writing in D, but language-agnostic, C and C++ answers would be useful to me, too) to ensure that all stack-allocated doubles that are accessed frequently are aligned on 8-byte boundaries? I'm currently optimizing some numerics code where misaligned stack-allocated doubles (only aligned on 4-byte boundaries) is causing about a 1.5 to 2x performance hit. , This is compiler specific. With GCC on x86, you'd use
code :

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Why does compiler align N byte data types on N byte boundaries?

Why does compiler align N byte data types on N byte boundaries?

By : john smith
Date : March 29 2020, 07:55 AM
seems to work fine I think I found the answer to my question. There might be two reasons for why the byte is padded between char and short and not after short.
1) Some architectures might have 2 byte instructions that fetch only 2 bytes from the memory. If such is the case, 2 memory read cycles are required to fetch the short.
Sprites not aligning to boundaries correctly

Sprites not aligning to boundaries correctly

By : FranzIsNotaCrime
Date : March 29 2020, 07:55 AM
it should still fix some issue The problem is that you're correcting each paddle's posy without adjusting its rect at the same time. posx and posy store the location of your sprite-- in this case, it's center-- but the position of what you see on-screen is determined by the rect. Because you add p#_movey, then update (which adjusts the rect), then, finally, make the posy correction for out-of-bounds values, rect remains at it's invalid location. Because you have adjusted posy, though, future p#_movey changes effect the correct location, not the invalid one (which is why your sprite remains O.B. until the movement key is released).
In short, this is what's going on:
code :
  # on the main loop...
for PADDLE in paddle_group.sprites():
    if PADDLE.posy > h - (PADDLE.height/2):
        PADDLE.posy = h - (PADDLE.height/2)
    elif PADDLE.posy < (PADDLE.height/2):
        PADDLE.posy = (PADDLE.height/2)

    PADDLE.rect.center = PADDLE.posx, PADDLE.posy
        ## ^ adding this line, which recenters the rect.
  # in class paddle(..) ...
def update(self, mov, tp):
    self.posy += mov * self.speed * tp
    self.posy  = max(self.height / 2, min(self.posy, h - (self.height / 2)))
        ## ^ Adding this line, which checks boundaries for posy.
        ## because you're doing it here, there's no need to do it again on the main loop.
    self.rect.center = self.posx, self.posy
Does aligning memory on particular address boundaries in C/C++ still improve x86 performance?

Does aligning memory on particular address boundaries in C/C++ still improve x86 performance?

By : Qin Bin
Date : March 29 2020, 07:55 AM
With these it helps The penalties are usually small, but crossing a 4k page boundary on Intel CPUs before Skylake has a large penalty (~150 cycles). How can I accurately benchmark unaligned access speed on x86_64 has some details on the actual effects of crossing a cache-line boundary or a 4k boundary. (This applies even if the load / store is inside one 2M or 1G hugepage, because the hardware can't know that until after it's started the process of checking the TLB twice.) e.g in an array of double that was only 4-byte aligned, at a page boundary there'd be one double that was split evenly across two 4k pages. Same for every cache-line boundary.
Regular cache-line splits that don't cross a 4k page cost ~6 extra cycles of latency on Intel (total of 11c on Skylake, vs. 4 or 5c for a normal L1d hit), and cost extra throughput (which can matter in code that normally sustains close to 2 loads per clock.)
Aligning a Stack pointer 8 byte from 4 byte in ARM assembly

Aligning a Stack pointer 8 byte from 4 byte in ARM assembly

By : kampfkegel
Date : March 29 2020, 07:55 AM
Hope this helps How do I align a stack pointer to 8 byte which is now 4 byte aligned in ARM .As per my understanding stack pointer is 4 byte aligned if it points to some address like 0x4 ,0x8,0x12 and 0x16 so on. , Due to the decreasing stack
Aligning memory on 16-byte and 32-byte boundaries

Aligning memory on 16-byte and 32-byte boundaries

By : C. J
Date : March 29 2020, 07:55 AM
like below fixes the issue
Are there ever any cases where 32-byte aligned memory is not also 16-byte aligned?
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